Field of the Invention
The present invention relates to a fabrication method of a semiconductor device having a high speed performance. Particularly, it relates to a vapor deposition method for forming an epitaxial silicon (Si) layer and a polycrystalline silicon layer over a silicon substrate which is partially covered with a silicon dioxide (SiO.sub.2) layer.
Description of the Related Art
In the recent LSI technology, reduction of parasitic capacitance of semiconductor devices has been an important factor to obtain a high speed performance of the devices. In a metal-oxide-semiconductor (MOS) field effect transistor (FET), for example, a structure of an elevated source-drain region is adopted. In a bipolar IC, an elevated base contact region made of polycrystalline silicon (hereinafter, referred to as `polysilicon`) is used in order to reduce the capacitance of a base region. A semiconductor device including the above-described MOS FET and bipolar transistor, such as a complementary MOS FET, is also fabricated.
FIG. 1 is a cross-sectional view schematically illustrating a structure of an MOS FET having elevated source-drain regions. In the figure, reference character, 51 designates a p.sup.- -type silicon substrate, for example, 52 designates a field oxide insulating layer, 53 designates a p-type channel region, 54 designates a gate insulating layer, 55 designates a gate electrode, 56 designates an n.sup.+ -type source region, 57 designates an n.sup.+ -type elevated source region, 58 designates an n.sup.+ -type drain region, 59 designates an n.sup.+ -type elevated drain region, ES designates an epitaxial silicon layer, and PS designates a polysilicon layer. In the following figures, like reference numerals and letters designate like parts through all the specification.
FIG. 2 is a cross-sectional view schematically illustrating a bipolar IC having an elevated base contact region. In FIG. 2 reference character, 51a designates a p.sup.- -type silicon substrate, 60 designates an n.sup.+ -type buried layer, 61 designates an n.sup.- -type collector region, 62 designates a p-type base region, 63 designates a p-type elevated base contact region, 64 designates an insulating layer, and 65 designates an n.sup.+ -type emitter region.
In the above semiconductor devices, the channel region 53, the source region 56, the drain region 58, and the base region 62 are formed in the epitaxial silicon layer ES, and the elevated source region 57, the elevated drain region 59, and the elevated base contact region 63 are formed on the polysilicon layer PS which is formed over the field oxide insulating layer 52. In a fabrication step of the devices, it is desirable that both of the epitaxial silicon layer ES and the polysilicon layer PS are simultaneously grown, respectively on the silicon substrate 51 or 51a and on the field oxide insulating layer 52.
FIG. 3 is a cross-sectional view of a semiconductor device in the above fabrication stage, illustrating a substantially schematic structure thereof. A polysilicon layer 5 is formed on a field oxide insulating layer 3 of silicon dioxide (SiO.sub.2) which is disposed on a silicon substrate 1, and an epitaxial silicon layer 4 having a top surface 6 is formed over an exposed surface 2 of the silicon substrate 1.
Referring to FIG. 3, a prior art vapor deposition technology for simultaneously growing the epitaxial silicon layer 4 and the polysilicon layer 5 over the silicon substrate 1 of the structure shown in the figure is described. In order to form a stable epitaxial silicon layer 4 and a polysilicon layer 5, the surface 2 of the silicon substrate 1 is activated prior to the vapor deposition. The activation process is implemented, for example, by bombarding the associated surface of the substrate with argon ions. The activation is considered to create silicon nuclei in a uniform distribution over the surfaces of the field oxide insulating layer 3 and the exposed silicon substrate 1.
Subsequently, vapor deposition to form the epitaxial silicon layer 4 and the polysilicon layer 5 simultaneously is performed under normal pressure, using a silicon source gas, such as silicon hydride (silane) gas, and a carrier gas such as hydrogen gas. One example of the vapor deposition condition is: gas pressure is normal (760 Torr), crystal growth temperature ranges from 950.degree. C. to 1050.degree. C., the silicon source gas is monosilane (SiH.sub.4), and the carrier gas is hydrogen (H.sub.2).
In the above-described prior art technology, there have been some disadvantages. FIG. 4 is a cross-sectional view, partially illustrating the epitaxial silicon layer ES and the polysilicon layer PS formed on the silicon substrate 51 and the field oxide insulating layer 52 respectively in a silicon vapor deposition step. The boundary surface (transition surface) between the epitaxial silicon layer ES and the polysilicon layer PS is apt to have a discontinuous portion having a sharp V-shaped groove or a crevasse C.sub.1, and the polysilicon layer PS formed on the field oxide insulating layer 52 tends to have a substantially rough surface containing a number of granular peaks and deep dimples C.sub.2. Such an uneven surface of the polysilicon layer PS causes unstable electrical connection to other circuit elements disposed on the substrate and the associated source region, drain region, or base region, degrading the performance of the device and reducing the fabrication yield of the device.
In another prior art vapor deposition technology, in order to improve the uneveness of the surface of the grown polysilicon layer, the surface of a silicon dioxide (SiO.sub.2) layer to be subject to silicon vapor deposition is covered previously by a silicon nitride (Si.sub.3 N.sub.4) film, whereby the above-described surface activation of the substrate by argon ion bombardment is unnecessary. The silicon vapor deposition gas employed is silane (SiH.sub.4) gas. The gas pressure is normal, and the crystal growth temperature is rather high ranging from 1100.degree. C. to 1150.degree. C. The result is favorable. However, this vapor deposition method requires complicated fabrication steps, increasing the fabrication cost, and causing various problems due to the high temperature treatment.
Furthermore, there has been a problem of shrinkage of the epitaxial silicon layer. As shown in FIG. 3, the top surface 6 of the epitaxial silicon layer 4 is shrinked as compared with the bottom surface 2, namely, the originally exposed silicon surface on the silicon substrate 1. As the result, the available active area for a semiconductor device to be formed is reduced, resulting in degrading the integration density of the device, and requiring an undesirable high accuracy of mask alignment in the subsequent fabrication steps. This phenomenon is considered to be caused by a lower growth rate of the epitaxial silicon layer than that of the polysilicon layer.
Before proceeding further, the crystal growth temperature of a silicon vapor deposition process will be described. In general, in a silicon vapor deposition process of a semiconductor device, the crystal growth temperature is desirable to be as low as possible, because high crystal growth temperature causes various problems. For example, in a device shown in FIG. 3, auto-doping of the relevant epitaxial silicon layer 4 is caused at a high crystal growth temperature which accelerates diffusion of dopants contained in the silicon substrate 1 into the epitaxial silicon layer 4, altering the dopant density of the epitaxial silicon layer 4. Consequently, the resulting electrical characteristics of the device may be undesirable, reducing the fabrication yield of the device. Meanwhile, in the above-described case where a field oxide insulating layer is formed on a silicon substrate in an earlier stage of the fabrication steps of a semiconductor device, thermal stress generated in a marginal zone along the interface between the field oxide insulating layer 3 and the silicon substrate 1 possibly causes some crystal defects. Subsequent high temperature treatments may increase the thermal stress substantially, further extending the crystal defects in the marginal zone, and thus degrading the quality of the device. In this point of view, reduction of the crystal growth temperature is a key point of the silicon vapor deposition process.
It is well known that a low pressure vapor deposition technique is effective to decrease the crystal growth temperature of the silicon vapor deposition for forming an epitaxial silicon layer on a silicon substrate. E. Krullmann et al., for example, reported in IEEE Transaction On Electron Devices, VOL. ED.29, No.4, Apr., 1982, on pages 491 to 497, that, in a silicon vapor deposition process, by reducing vapor deposition gas pressure from 760 Torr to 40 Torr, the crystal growth temperature could be lowered by approximately 100.degree. C. to 150.degree. C., whereby monosilane (SiH.sub.4) and dichlorosilane (SiH.sub.2 Cl.sub.2) were employed as the silicon source gas.
In a Japanese Laid Open Patent Application, No. 159421/1987, one of the inventors of the present invention and others proposed a vapor deposition method for forming an epitaxial silicon layer over a silicon substrate, utilizing a silicon dioxide (SiO.sub.2) layer as a mask, by using disilane (Si.sub.2 H.sub.6) gas as a silicon source gas. A low crystal growth temperature of 700.degree. C. is obtained under a gas pressure of 3 Torr.
Further, one of the inventors of the present invention and others reported a low pressure vapor phase silicon epitaxy using disilane (Si.sub.2 H.sub.6) in Extended Abstracts of the 18th International conference on Solid State Devices and Materials, Tokyo, 1986, on pages 49-52. The dissociation energy of the disilane (Si.sub.2 H.sub.6) is smaller than that of the monosilane (SiH.sub.4) gas conventionally used in a silicon vapor deposition. It is considered that the low dissociation energy of the disilane (Si.sub.2 H.sub.6) serves to provide the dissociated silicon atoms with sufficient energy to migrate over the deposited surface freely. This explains why the disilane (Si.sub.2 H.sub.6) gas enables the silicon epitaxial growth under a low crystal growth temperature. However, a vapor deposition method for simultaneously forming the epitaxial silicon layer and the polysilicon layer at a low crystal growth temperature has not been realized as yet.